Analysis of First- and Second-Order Digital DS Modulator Used in Fractional-N PLLs
Abstract
In this paper, we analyze for the first time behavior in the time domain of the accumulated quantization error induced by the first- and second-order digital DeltaSigma modulator (DSM). The DSM is adopted in fractional-N PLLs to dither frequency division factor. From the analysis, difference in behavior of the accumulated quantization error in the two cases is clearly explained. Furthermore, by mean of this, the reason of using second-order DSM is required for the calibration loop of digital/time converter canceling the quantization error is revealed. It also explains why there is variation in convergence time even with the second-order DSM when fractional part of the division factor changes.
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References
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[18] K. Hosseini and M. P. Kennedy, “Mathematical analysis of a prime modulus quantizer mash digital delta–sigma modulator,” IEEE Trans. Circuits and Systems II, vol. 54, no. 12, pp. 1105–1109, Dec. 2007.
[19] S. B. Sleiman and M. Ismail, “Multimode reconfigurable digital DS modulator architecture for fractional-n plls,” IEEE Trans. Circuits and Systems II, vol. 57, no. 8, pp. 592–596, Aug. 2010.
[20] J. Song and I.-C. Park, “Spur-free mash delta-sigma modulation,” IEEE Trans. Circuits and Systems I, vol. 57, no. 9, pp. 2426–2437, Sep. 2010.
[21] K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital Delta-Sigma Modulators. Springer, Jul. 2011.
[22] F. Bizzarri, A. Brambilla, and S. Callegari, “Efficient and reliable small-signal estimate of quantization noise contribution to phase noise in DS fractional- n pll,” IEEE Trans. Circuits and Systems I, vol. 64, no. 6, pp. 1494–1503, Jun. 2017.
[23] V. Mazzaro and M. P. Kennedy, “Observations concerning “horn spurs” in a mash-based fractional-n cp-pll,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov. 2019.
[24] B. Fitzgibbon, M. P. Kennedy, and F. Maloberti, “Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input,” IEEE
Trans. Circuits and Systems I, vol. 58, no. 9, pp. 2137–2148, 2011.
[25] K. Hosseini and M. P. Kennedy, “Maximum Sequence Length MASH Digital Delta–Sigma Modulators,” IEEE Trans. Circuits and Systems I, vol. 54, no. 12, pp. 2628 – 2638, Dec. 2007.
[26] K. Hosseini and M. P. Kennedy, “Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators,” IEEE Trans. Circuits and Systems II, vol. 55, no. 11, pp. 1104 – 1108, Dec. 2008.
[2] W. Bae, “State-of-the-art circuit techniques for low-jitter phase-locked loops: Advanced performance benchmark fom based on an extensive survey,” IEEE International Symposium on Circuits and Systems (ISCAS), May. 2021.
[3] B. Miller and R. J. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 3, pp. 578–583, Jun. 1991.
[4] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta–sigma modulation in fractional-n frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553–559,
May. 1993.
[5] W. Yu, K. S. Kim, and S. H. Cho, “A 0.22 ps rms integrated noise 15 mhz bandwidth fourth-order DS time-to-digital converter using time-domain error-feedback filter,” IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1251–1262, May. 2015.
[6] T. M. Vo, S. Levantino, and C. Samori, “Analysis of Fractional-N Bang-Bang Digital PLLs using Phase Switching Technique,” in 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Jun. 2016, pp. 1–4.
[7] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita, “A 2.9-to-4.0GHz Fractional-N Digital PLL with Bang-Bang Phase Detector and 560fsrms Integrated Jitter at 4.5mW Power,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2745–2758, Dec. 2011.
[8] T. M. Vo, C. Samori, A. L. Lacaita, and S. Levantino, “A Novel Segmentation Scheme for DTC-Based DS Fractional-N PLL,” in Proc. IEEE Symposium on Circuits and Systems (ISCAS), May 2017, pp. 242–245.
[9] H. Liu et al., “A 0.98mw fractional-n adpll using 10b isolated constant-slope dtc with fom of -246db for iot applications in 65nm cmos,” IEEE ISSCC Dig. Tech. Papers, Feb. 2018.
[10] T. M. Vo, C. Samori, and S. Levantino, “A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs,” Proc. IEEE Symposium on Circuits and Systems (ISCAS), pp. 1–4, May. 2018.
[11] W.Wu et al., “A 28-nm 75-fsrms analog fractional- n sampling pll with a highly linear dtc incorporating background dtc gain calibration and reference clock duty cycle correction,” IEEE J. Solid-State Circuits, vol. 54, no. 5, pp. 1254–1265, May. 2019.
[12] V. Govindaraj et al., “Dtc-assisted all-digital phase-locked loop exploiting hybrid time/voltage phase digitization,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019.
[13] T. M. Vo, “A novel parallel dtc segmentation scheme for fractional-n digital plls,” Journal of Science and Technology: Issue on Information and Communications Technology, vol. 18, no. 4.2, pp. 1–7, 2020.
[14] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for DS fractional-n frequency synthesizers allowing straightforward noise analysis,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028–1038, Aug. 2002.
[17] M. J. Borkowski, T. A. D. Riley, J. Hakkinen, and J. Kostamovaara, “A practical DS modulator design method based on periodical behavior analysis,” IEEE Trans. Circuits and Systems II, vol. 52, no. 10, pp. 626–630, Oct. 2005.
[15] M. Kozak and I. Kale, “Rigorous analysis of delta–sigma modulators for fractional-n pll frequency synthesis,” IEEE Trans. Circuits and Systems I, vol. 51, no. 6, pp. 148–1162, Jun. 2004.
[16] P. Heydari, “Characterizing the effects of the pll jitter due to substrate noise in discrete-time delta-sigma modulators,” IEEE Trans. Circuits and Systems I, vol. 62, no. 6, pp. 1073–1085, Jun. 2005.
[18] K. Hosseini and M. P. Kennedy, “Mathematical analysis of a prime modulus quantizer mash digital delta–sigma modulator,” IEEE Trans. Circuits and Systems II, vol. 54, no. 12, pp. 1105–1109, Dec. 2007.
[19] S. B. Sleiman and M. Ismail, “Multimode reconfigurable digital DS modulator architecture for fractional-n plls,” IEEE Trans. Circuits and Systems II, vol. 57, no. 8, pp. 592–596, Aug. 2010.
[20] J. Song and I.-C. Park, “Spur-free mash delta-sigma modulation,” IEEE Trans. Circuits and Systems I, vol. 57, no. 9, pp. 2426–2437, Sep. 2010.
[21] K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital Delta-Sigma Modulators. Springer, Jul. 2011.
[22] F. Bizzarri, A. Brambilla, and S. Callegari, “Efficient and reliable small-signal estimate of quantization noise contribution to phase noise in DS fractional- n pll,” IEEE Trans. Circuits and Systems I, vol. 64, no. 6, pp. 1494–1503, Jun. 2017.
[23] V. Mazzaro and M. P. Kennedy, “Observations concerning “horn spurs” in a mash-based fractional-n cp-pll,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov. 2019.
[24] B. Fitzgibbon, M. P. Kennedy, and F. Maloberti, “Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input,” IEEE
Trans. Circuits and Systems I, vol. 58, no. 9, pp. 2137–2148, 2011.
[25] K. Hosseini and M. P. Kennedy, “Maximum Sequence Length MASH Digital Delta–Sigma Modulators,” IEEE Trans. Circuits and Systems I, vol. 54, no. 12, pp. 2628 – 2638, Dec. 2007.
[26] K. Hosseini and M. P. Kennedy, “Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators,” IEEE Trans. Circuits and Systems II, vol. 55, no. 11, pp. 1104 – 1108, Dec. 2008.
Published
2021-12-31
How to Cite
VO, Minh Tuan.
Analysis of First- and Second-Order Digital DS Modulator Used in Fractional-N PLLs.
Journal of Science and Technology: Issue on Information and Communications Technology, [S.l.], v. 19, n. 12.2, p. 10-16, dec. 2021.
ISSN 1859-1531.
Available at: <http://ict.jst.udn.vn/index.php/jst/article/view/137>. Date accessed: 26 apr. 2024.
doi: https://doi.org/10.31130/ict-ud.2021.137.
Section
Articles
